1. Field of the Invention
This invention relates to integrated circuit processing and, more particularly, to rapid thermal processing and reflow operations.
2. Description of Related Art
As semiconductor device dimensions become increasingly finer, certain traditional integrated circuit manufacturing techniques have become increasingly ineffective. For example, contacts through a dielectric layer have long been made by etching vias through the dielectric layer and then filling the vias with metal deposited via chemical vapor deposition or sputtering methods. With each new generation of integrated circuit, the aspect ratio of vias (i.e., the ratio of depth to width) has typically increased while the cross-sectional area of the opening has typically decreased. As a consequence of this trend, it has become increasingly difficult to completely fill contact vias within integrated circuits of recent manufacture with deposited metal. If contact vias are not completely filled with metal, contact with an underlying conductive layer or junction may fail, thus rendering the integrated circuit non-functional.
Another problem related to small device geometries is that of decreasing depth of focus range during photoresist exposure to radiation at the high-frequency end of the UV band. Excessive topographical surface variations can lead to varying degrees of exposure at different focus levels. Out of focus features may not print at all, which may result in non-functional circuitry. Therefore, wafers are often planarized prior to photoresist deposition and exposure in order to increase circuit quality.
Still another problem related to shrinking device dimensions is that of void formation between elevated features such as parallel word lines during the chemical vapor deposition of a silicon dioxide interlevel dielectric layer.
All of the aforementioned problems can be mitigated by ref lowing the deposited material. During reflow, the material is heated to a temperature where it becomes plastically deformable (i.e., flowable). When a metal layer that has been deposited over contact via openings is reflowed, gravity assists in the filling of contact vias as molten metal from the deposited metal layer seeks the lowest level. Likewise, when a silicon dioxide layer is subjected to a reflow step and becomes flowable, voids between elevated features can be eliminated. A further benefit of reflow is the reduction in topographical variations on the wafer's surface. Reflow operations are also used to densify deposited silicon dioxide layers, which tend to be less dense than those which are thermally grown. Such use is unrelated to the decrease in device dimensions.
During the fabrication process, an integrated circuit is subjected on numerous occasions to elevated temperature. Generally, the elevated temperature is required to effect a necessary step in the fabrication process. For example, oxidation of silicon, aluminum metalization, implant activations, chemical vapor deposition of silicon dioxides, and reflow operations are generally performed at temperatures in excess of 500 degrees centigrade. Although a certain amount of exposure to elevated temperatures is required both to activate implanted ions and to cause them to diffuse within the implanted material, excessive exposure to elevated temperature is injurious to integrated circuits. Excessive exposure to elevated temperature is irreversible, and can cause the overlapping and counter-doping of adjacent implants having opposite conductivity types, as well as the diffusion of dopants from source/drain regions of field-effect transistors into the channel regions. The overlapping and counter-doping of opposite, adjacent implants can obliterate junctions. Out-diffusion of dopants into the channel regions can result in transistor leakage. Greater out-diffusion will, at some point, short the source/drain regions of a transistor together and completely destroy the functionality of the circuit. The exposure of integrated circuits to heat is analogous in two respects to the exposure of living organisms to ionizing radiation. Not only is exposure cumulative, but at some exposure level, the organism will die. Each integrated circuit device has an optimum thermal exposure level that is generally referred to as the circuit's thermal budget. Actual thermal exposure levels which either exceed or fall short of the thermal budget may adversely affect circuit performance. The actual thermal exposure level is calculated by summing all individual occurrences of thermal exposure during the fabrication process, each occurrence being a function of both exposure time and exposure temperature. Although thermal exposure with respect to time is a linear function, thermal exposure with respect to temperature is not, as the rate of diffusion increases exponentially with increasing temperature.
As device geometries are shrunk for new generations of integrated circuits, thermal budgets must be lowered by a corresponding amount. Unless the process is modified to reflect these reduced thermal budgets, it will become increasingly difficult to stay within those budgets.
In order to reduce the thermal budget of integrated circuits which are subjected to reflow operations, rapid thermal processing is typically used for such operations. Rapid thermal processing generally involves rapidly and uniformly heating the surface of a semiconductor wafer with a radiant heat source. Infrared lamps are often used for a radiant heat source. Because of thermal budget limitations, circuits can seldom be subjected to rapid thermal processing in conventional systems for a period sufficient to fully solve the problem for which the reflow operation is undertaken, as the characteristic viscosities of the molten materials prevent rapid flow. Thus, a reflow step seldom succeeds in eliminating all topographical variations on the surface of a wafer or in completely filling contact via openings. In order to further reduce topographical variations, further planarization using a chemical etchback, mechanical polishing or chemical mechanical planarization (a combination of chemical etching and mechanical polishing) is generally required. In order to ensure that contact via openings are adequately filled with metal, the openings are typically made larger than the critical dimension (i.e., the smallest printable size) to reduce the effect of viscosity on flow, thus wasting precious wafer real estate.
It is clear that additional advances will be required to maintain the usefulness of reflow operations as device dimensions are reduced still further.